module ir(
    input  clk,
    input  ld_ir,
    input  [7:0]a,
    output reg [7:0]x
);       

//negedge triggered
always@(negedge clk)
begin
//insruction: ld_ir= 1, data: ld_ir=0;  
    if(ld_ir) x<=a;
    else ;
end
endmodule
